Non-volatile memory systems, such as memory cards, solid state drives (SSDs) or embedded non-volatile memories (such as iNAND), are typically formed of a controller circuit and a number of memory chips. These memory chips are connected to the controller over a bus structure, where it is common for multiple memory chips to share a common bus structure having shared ready/busy (RB) line. For example, a single ready busy line can be shared by up to 16 dies, where only the actively selected die (including the chip enable (CE)) can use the ready/busy line at any given time. A baseline method of checking if a die is ready is by selecting the die and then sampling or polling the ready/busy signal. An alternative design is to select a die then use the check status command across the data bus to check a die's status. However, constant polling is inefficient and leads to higher power consumption. Cycling through dies selecting dies to check the status adds latency and increases power. In older memory systems, as instructions for similar operations were typically issued serially through the set of dies, this was not so much of limitation, but as memory die become more autonomous and their operations vary more in timing, this situation has become limiting on memory systems.